1. Field of the Invention
The present invention relates to a current-cell type digital-to-analog converter (hereinafter referred to as “D/A converter”) for converting a digital code to the analog voltage corresponding to the digital code using a timing generating circuit, especially, a D/A converter using a timing generating circuit having a simplified circuit configuration to improve the glitch or the settling time thereof.
This application is a counterpart of Japanese application, Ser. No. 043262/2006, filed Feb. 21, 2006, the subjects matter of which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, as a technology concerned, about a D/A converter for improving the glitch or the settling time thereof, there is a description of, for example, the following documents.    Patent Document 1: Japanese patent laid-open number 2003-115761 (Document D1).    Patent Document 2: Japanese patent laid-open number H10-3791 (Document D2).
FIG. 7 is a view of configuration diagram of the main parts of the conventional current-cell type D/A converter described in the Document D1.
The above mentioned current-cell type D/A converter includes a plural of current cells 10-0, 10-1, 10-2, - - - having a plural of weighted current values of I20, I21, I22, - - - , respectively. The above plural of current cells 10-, 10-1, 10-2, - - - are connected in parallel between the plus source voltage node (hereinafter referred to as “VDD”) and the output line 14 and between the VDD node and the ground node (hereinafter referred to as “GND”). In FIG. 7, the plural of current cells 10-0. 10-1, 10-2, - - - are only shown. Furthermore, a driver having a couple of switch-control-signal generating circuits 20-1, 20-2 for driving the current cell 10-0 is connected to the current cell 10-0. Drivers for driving other current cells 10-1, 10-2, - - - are connected to the current cells 10-1, 10-2 - - - , respectively, as well.
For example, the current cell 10-0 includes a constant current source 11 for applying a weighed current value I20 and two p-type MOS transistors 12, 13 (hereinafter referred to as “PMOS”) of a differential switch. The constant current source 11 is connected between the VDD node and a common node N11, and the PMOS 12 is connected between the above common node N11 and an output line 14, furthermore, the PMOS 13 is connected between the common node N11 and the GND. Other current cells 10-1, 10-2, - - - being not shown in the figures have the same configurations as the above-mentioned configuration. An output terminal OUT is connected to one end of the output line 14, and a resistor 15 for current-to-voltage conversion (hereinafter referred to as “I/V conversion”) is connected between the above output terminal OUT and the GND.
A couple of switch-control-signal generating circuits 20-1, 20-2 drive the current cell 10-0, as mentioned before. The switch-control-signal generating circuit 20-1 is connected to an output side of an inverter 25 for inverting a signal of digital code D being inputted from an input terminal IN, and is configured to output a switch-control signal S20-1 having the predetermined timing to a gate of PMOS 12 and turn on/off the above PMOS 12. Meanwhile, the switch-control-signal generating circuit 20-2 has the same circuit configuration as the above switch-control-signal generating circuit 20-1 to output the switch-control signal S20-2 having the predetermined timing to the gate of PMOS 13, based on the signal of digital code D, and turn on/off the above PMOS 13.
The switch-control-signal generating circuit 20-2 consists of a master-side latch circuit 21, a selector 22, a slave-side latch circuit 23. The master-side latch circuit 21 is a circuit for holding the digital code signal D, synchronized with complementary latch signals LA, LAB. The master-side latch circuit 21 consists of a N-channel type MOS transistor (hereinafter referred to as “NMOS”) and an inverter, and the selector 22 is connected to the output side thereof. The selector 22 is a circuit for selecting one of two delayed signals R, F corresponding to a signal latched by the latch circuit 21 and outputting the selected signal thereof. The selector 22 consists of a not-and (NAND) logic gate and an inverter, and the slave-side latch circuit 23 is connected to the output side thereof. The slave-side latch circuit 23 is a circuit for outputting the switch control signal S20-2 using the signal selected by the selector 22 and the above complementary signal and has the same circuit configuration as the master-side latch circuit 21.
In the D/A converter having the above mentioned configuration, the switch-control signals S20-1, S20-2, - - - inputted to each of the input terminal IN to control the PMOSs 12, 13, - - - for differential switches in each of the current cells 10-0, - - - are generated by the switch-control-signal generating circuits 20-1, 20-2, - - - and each of the current cells 10-0, - - - supplies currents from the constant current sources 11, - - - , to the GND side or the output line 14 side, corresponding to the switch-control signals S20-1, S20-2, - - - . Subsequently, all the currents supplied to the output line 14 side are added and converted to voltages by the resistor 15 for I/V conversion. Then, the analog voltages thereof corresponding to the digital codes D, - - - are outputted from the output terminal OUT.
Each of the current cells 10-0, - - - is configured to have a period when the switch-control signals S20-1, 20-2, - - - become low level (hereinafter referred to as “L-level”) at switching timing thereof, that is, the PMOSs 12, 13, - - - are simultaneously turned on. Consequently, in each of the current cells 10-0, - - - , glitches or variations of settling time can be prevented at turning on/off timings of the PMOSs 12, 13, - - - .